从同学那里拷来的代码，VHDL设计数码管显示电路：
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan_led4 is port( scan_clk:in std_logic; arh,arl,bush,busl:in std_logic_vector(3 downto 0); seg7:out std_logic_vector(6 downto 0); bsg:out std_logic_vector(3 downto 0)); end scan_led4; architecture rtl of scan_led4 is signal seg_wire:std_logic_vector(3 downto 0); signal bsg_wire:std_logic_vector(3 downto 0); type st is (k1,k2,k3,k4); signal st_nxt:st; --st类型的信号？ --模4计数器 begin scan_st:process(scan_clk,st_nxt) begin if(scan_clk'event and scan_clk='1') then case st_nxt is when k1=> st_nxt<=k2; when k2=> st_nxt<=k3; when k3=> st_nxt<=k4; when k4=> st_nxt<=k1; end case; end if; end process; --段选和位选 scan_o:process(st_nxt,arh,arl,bush,busl) begin case st_nxt is when k1=> seg_wire<=arh; bsg_wire<="1000"; --计数值1时，1号数码管显示ar高四位 when k2=> seg_wire<=arl; bsg_wire<="0100"; --计数值2时，2号数码管显示ar低四位 when k3=> seg_wire<=bush; bsg_wire<="0010"; --计数值3时，3号数码管显示bus高四位 when k4=> seg_wire<=busl; bsg_wire<="0001"; --计数值4时，4号数码管显示bus低四位 end case; end process; --7段译码 seg7<="1111110" when seg_wire=x"0" else "0110000" when seg_wire=x"1" else "1101101" when seg_wire=x"2" else "1111001" when seg_wire=x"3" else "0110011" when seg_wire=x"4" else "1011011" when seg_wire=x"5" else "1011111" when seg_wire=x"6" else "1110000" when seg_wire=x"7" else "1111111" when seg_wire=x"8" else "1111011" when seg_wire=x"9" else "1110111" when seg_wire=x"a" else "0011111" when seg_wire=x"b" else "0001101" when seg_wire=x"c" else "0111101" when seg_wire=x"d" else "1001111" when seg_wire=x"e" else "1000111" when seg_wire=x"f" else "0000000" ; bsg<=bsg_wire; end rtl; |
对比自己以前写的数码管显示的vhdl代码，发现自己简直弱爆了，没有一点整体设计思想，单纯的把电路图各个部件翻译成vhdl代码，然后在连接起来，而上面的代码是整体描述了数码管显示电路，其实数码管显示电路还是比较简单的，输入两组，输出两组。输入就是一个clk时钟信号，还有要显示的数据。输出就是一个段选和一个位选。
看来vhdl很重要啊，掌握了会比电路图简单。
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