2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

use ieee.std_logic_1164.all;

entity decoder37 is

port( data:in std_logic_vector(2 downto 0);

seg:out std_logic_vector(6 downto 0));

end decoder37;

architecture rtl of decoder37 is

begin

process(data)

begin

case data is

when "000" =>seg<="0000001";

when "001" =>seg<="0000010";

when "010" =>seg<="0000100";

when "011" =>seg<="0001000";

when "100" =>seg<="0010000";

when "101" =>seg<="0100000";

when "110" =>seg<="1000000";

when others =>null;

end case;

end process;

end rtl;